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VERSION:2.0
PRODID:-//ctl.byu.edu//NONSGML iCalcreator 2.4.3//EN-US
X-WR-CALNAME;LANGUAGE=en-US:EC EN 451 Assignments
BEGIN:VEVENT
UID:20120516T204729MDT-8307Z09bM2@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120111
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW#1 - static CMOS\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8318ToZB4u@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120116
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: No class
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-83266EZuKk@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120118
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #2 - static CMOS and desig
 n rules\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-83341mmIeZ@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120120
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: Lab 1 - schematic capture\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-83403ctCUK@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120125
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #3 - stick diagrams and si
 zing\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8346DbNHRe@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120127
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments:  Lab 2 - layout\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8352Zmg860@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120201
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #4 - Pass transistors and 
 economics\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8359KDxLSU@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120215
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments:  HW #6 - RC delay\, character
 ization\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8366BWX7vF@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120217
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: Lab 3 - characterization\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8374osdd40@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120220
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: No class
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8379BFHZz2@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120222
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments:  HW #7 - Logical effort\, sca
 ling\, model limits\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8384XN2Krg@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120229
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #8 - Logical effort\, powe
 r\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8389tWscRm@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120206
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: Midterm 1 opens\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8394HnKus9@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120208
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #5 - DC transfer\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8400jcv7xs@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120208
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: Midterm 1 closes\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8405vztJ6i@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120314
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #10 - CMOS variants\, pseu
 do-NMOS\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8411flfSAh@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120319
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: Midterm 2 opens\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8417nxlaGu@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120321
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #11 - Dynamic logic\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8422EvNUbL@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120321
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: Midterm 2 closes\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8428svL6VI@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120328
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #12 - sequential elements
 \n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8433Bv2Dg7@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120330
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: Lab 4 - sequential element de
 sign and characterization\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8438GwsjGV@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120307
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #9 - Wires\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8443LFLAJ7@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120411
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: Lab 5 - chip assembly\n
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8449mdfrmT@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120412
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: No class
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8454IiVsTg@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120413
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: No class
END:VEVENT
BEGIN:VEVENT
UID:20120516T204729MDT-8460FmHpxJ@ctl.byu.edu
DTSTAMP:20120516T024729Z
DTSTART;VALUE=DATE:20120404
SUMMARY;LANGUAGE=en-US:EC EN 451 Assignments: HW #13 - sequential timing\, 
 timing analysis\n
END:VEVENT
END:VCALENDAR