Electrical and Computer Engineering 451

Winter Semester 2012

Section 1: 490 CB on M W Th F at 01:00 pm - 01:50 pm

Instructor Information

Instructor: David PenryOffice: CB 445Office Hours: M F 11 am - 12 pm

Office Hours:

W 2 - 3 pm

Office Hours:

M – F by appointment or you can drop in, but not between 10 am and 11 amOffice Phone: 801-422-7665Email: dpenry@ee.byu.edu

TA Information

Name: Danny Savory
Location: 4th floor CAEDM lab
Hours: M W F 3pm - 7pm

Hours:

T Th 2pm - 6pm

Course Information

Texts & Materials

Required Vendor Price (new) Price (used)
CMOS VLSI DESIGN 4E By WESTE, N ISBN: 9780321547743 BYU $132.00 $99.00
 
Colored pencils/pens

You will need to obtain colored pencils or pens by the second week of class.  The colors you will need are: black, red, blue, yellow, green, and purple or pink.

Description

This course provides you with a thorough introduction to the techniques and tools used in designing digital circuits in CMOS technologies.  This course will provide the opportunity to develop skills used by circuit and layout designers.  Furthermore, it will develop your understanding of how CMOS technology characteristics affect the design of digital systems.

Prerequisites

  • ECEn 313 - Analog Circuit Design or equivalent
  • ECEn 320 - Digital Systems or equivalent

Classroom Procedures

  • This course requires four hours of in-class work each week.  The MWF classes will typically consist of lecture and discussion.  The Thursday class will be a recitation section conducted by the TA or the instructor.  It will not necessarily take place every week, but there will be some sessions; these are shown on the calss schedule.  Explanations of how to use the CAD tools needed to complete lab assignments will take place during the recitation session.
  • The textbook is intended to complement the lecture.  It will likely not be possible to perform well in this class withoput both attending class and reading the textbook.  I suggest that you skim the readings for a given class period before that class to prepare yourself for the lecture and then read in more detail afterwards to better fix the concepts in your mind.
  • You will need access to Blackboard to access some course materials.  All course announcements and corrections to lab assignments and materials will be made on Blackboard.  You are responsible for knowing any information which is posted on Blackboard.

Attendance Policy

While I do not include an attendance portion in the grade, I do expect you to attend all class periods.  From the official university policy:

 

"You are expected to attend classes for which you are registered.  Each class instructor may determine the relationship of class attendance to the final grade for the course.  Officially excused absences are required only when you are away representing the university on official business.  All officially excused absences must be excused through the dean of students.

 

Faculty should tell you what relationship attendance has to your final grade for the course, but you must take the responsibility for your actions.  It is not necessary for the instructor to report absences to the office of the dean of students unless he or she has knowledge of an accident or illness that is causing the absence.  Notification to teachers of emergency absences (death in the family, serious illness, etc.) is your responsibility."

Grading Policies

Grade Breakdown

The grading is broken down as follows:

Assignment Percentage of grade
13 Homeworks 20 (evenly weighted)
5 Labs 40 (evenly weighted)
2 Midterms 20 (10 each)
Final Exam 20
Lab Assignments

The labs are a major emphasis in this course; all lab assignments must be completed to receive a passing grade (C- or better) in this class. Unless an exception is approved in advance, the final deadline for all lab submissions is noon on the last day of classes for the semester or term.

 

Labs should be completed with a lab partner.  Labs are due before midnight on the assigned day. Late labs will be docked 20 percent per weekday (Monday-Friday) to a maximum of 80 percent. (In other words, no matter how late you finish a lab, you can still get 20 percent if the late submission is error free.)  You will each be allowed a total of 4 late days without penalty for labs over the course of the entire semester or term. Use them wisely!  Free late days will be applied in chronological order.

 

Regardless of the points given for each lab, all labs will be weighted equally in the calculation of final grades.

 

The ECEn department Linux machines in CB 425 will be used for the labs in this class. You will need a CAEDM account to access these machines. For more information about the "spice" machines and CAEDM accounts, click on the "computer help" link on the ECEn home page.

 

Homework

There will be thirteen homework assignments.  These assignments are given after a concept is discussed to give you practice employing the concept and solving design problems.  A typical homework assignment will consist of a few problems from the book.  Each sub-problem (typically a separate answer you are asked to report) is graded separately.  Correct answers will receive 3 points, reasonable attempts at an answer will receive 2 points, and feeble attempts (such as a number with no explanation of your work) will receive 0 points.  Homeworks are to be turned in by midnight on the due date in the homework box.  Late homeworks will be accepted up to three weeks after they are due with a 50% penalty.  You may collaborate with other students as you do your homework, but if you do, you must report who you collaborated with on your homework assignment.

 

Regardless of the points allocated per assignment, all homework assignments will be weighted equally in the calculation of final grades.

 

Exams

Two closed-book midterms will be given in the testing center on the dates indicated in the class schedule. The final exam will cover all material covered over the semester and will be given in the testing center. The format of all exams is multiple choice with one correct answer.  Midterms should take about two hours and the final about three hours.

 

You are responsible to schedule your time to take all exams; they will be available in the testing center over multiple days to give you some flexibility. Do not miss exams: only under very unusual circumstances will you be given an opportunity to make up an exam that you miss. Plan your travel and interview trips around your exams.

Tracking Your Scores

A summary of your scores on all graded assignments and exams will be posted on BYU Gradebook. Please check your posted scores regularly to make sure they are correct. In the absence of any reports of errors, scores will be assumed correct one week after they are posted.
 

Mistakes in Grading

Unfortunately, mistakes do sometimes occur in grading.  If you feel that there is an error in grading, submit an explanation to the instructor in writing with the entire assigment attached no later than one week after the assigment is returned.  The entire assigment may be regraded at the discretion of the instructor.  I require the explanation in writing so that the error is documented and to allow you the opportunity to give measured, reasoned, non-emotional arguments.

Learning Outcomes

  • CMOS Circuits

    Ability to analyze CMOS circuits.

  • Translate Digital Logic to CMOS Circuits

    Ability to translate digital logic to CMOS circuits to achieve desired behavior and performance requirements.

  • CMOS Layout

    Ability to perform CMOS layout.

  • Tools

    Ability to use eCAD tools for CMOS design.

  • Techniques

    Ability to characterize timing and noise in CMOS circuits.

Grading Scale

A[93.3, 100]B-[80, 83.3)D+[66.6, 70.0)
A-[90.0, 93.3)C+[76.6, 80)D[63.3, 66.6)
B+[86.6, 90)C[73.3, 76.6)D-[60, 63.3)
B[83.3, 86.6)C-[70, 73.3)Ebelow 60

Schedule

Course Schedule

Date ExportTopics ExportAssigned readings ExportAssignments Export

W - Jan 4

Course introduction

MOS transistors

Design flows

1.1 - 1.2

1.3

1.6, 14.1 - 14.4

-

Th - Jan 5

No class

--

F - Jan 6

Static CMOS gates

1.4 - 1.4.5

-

M - Jan 9

Static CMOS gates

--

W - Jan 11

Fabrication

1.5.1 - 1.5.2

3.2 is optional: read if you are really interested in the manufacturing process

HW#1 - static CMOS

Th - Jan 12

Cadence setup and schematic editor

--

F - Jan 13

Layout design rules

1.5.3 - 1.5.4, 3.3, 3.5 - 3.6

-

M - Jan 16

Martin Luther King Jr. Holiday-No class

W - Jan 18

Stick diagrams and size estimation

1.5.5, 14.7 (found online)

HW #2 - static CMOS and design rules

Th - Jan 19

Cadence layout tools

--

F - Jan 20

Stick diagrams, cont.

-

Lab 1 - schematic capture

M - Jan 23

Voltage model and pass transistors

1.4.6 - 1.4.8, 2.5.4

-

W - Jan 25

Pass transistors, cont.

Design economics

14.5

HW #3 - stick diagrams and sizing

Th - Jan 26

Open lab

--

F - Jan 27

Design Economics, cont.

-

Lab 2 - layout

M - Jan 30

CMOS device characteristics

2.1 - 2.2

-

W - Feb 1

DC transfer

2.5

HW #4 - Pass transistors and economics

Th - Feb 2

Midterm review

--

F - Feb 3

DC transfer, continued

--

M - Feb 6

RC delay models

4.1 - 4.3.6

Midterm 1 opens

W - Feb 8

Characterization

RC delay models, continued

8.4.5

HW #5 - DC transfer

Midterm 1 closes

Th - Feb 9

Cadence simulation tools

--

F - Feb 10

Verification and test

15.1 - 15.5

-

M - Feb 13

Logical effort: motivation and derivation

4.4

-

W - Feb 15

Logical effort: size optimization

4.5.1

HW #6 - RC delay, characterization

Th - Feb 16

Open lab

--

F - Feb 17

Transistor model limits

New transistor technologies

Scaling

2.4

3.4.1, 3.4.4

7.4

Lab 3 - characterization

M - Feb 20

Presidents Day Holiday-No class

T - Feb 21

Logical effort: path optimization

4.5.2 - 4.5.5

-

W - Feb 22

Logical effort: problems

-

HW #7 - Logical effort, scaling, model limits

Th - Feb 23

Q & A

--

F - Feb 24

Power

5.1 - 5.3, 5.5, 13.3

-

M - Feb 27

Wire delays

6.1 - 6.3.1

-

W - Feb 29

Wire engineering

6.4.1 - 6.4.3

HW #8 - Logical effort, power

Th - Mar 1

Q & A

--

F - Mar 2

Noise

6.3.3 - 6.3.4

-

M - Mar 5

Static CMOS variants

9.2.1, 9.2.5

-

W - Mar 7

Pseudo-NMOS

Dynamic CMOS

9.2.2

9.2.4

HW #9 - Wires

Th - Mar 8

Open Lab

--

F - Mar 9

I/O and packaging

13.2, 13.6

-

M - Mar 12

Dynamic CMOS

--

W - Mar 14

Dynamic CMOS

-

HW #10 - CMOS variants, pseudo-NMOS

Th - Mar 15

Midterm review

--

F - Mar 16

Floorplanning, Place and Route

1.10

-

M - Mar 19

Sequential element design

10.3

Midterm 2 opens

W - Mar 21

Sequential element characterization

10.4.2, 10.6

HW #11 - Dynamic logic, floorplanning

Midterm 2 closes

Th - Mar 22

Simulation for sequential element characterization

--

F - Mar 23

Clock distribution

13.4 - 13.5

-

M - Mar 26

Sequential timing methodology

10.1 - 10.2

-

W - Mar 28

Sequential timing, cont.

-

HW #12 - sequential elements

Th - Mar 29

Open Lab

--

F - Mar 30

Timing analysis and closure

Documentation

4.6

14.6

Lab 4 - sequential element design and characterization

M - Apr 2

Array design and memory cells

12.1 - 12.4

-

W - Apr 4

Reliability

7.1 - 7.3, 7.5.2, 7.6, 12.8

HW #13 - sequential timing, timing analysis

Th - Apr 5

Cadence router

--

F - Apr 6

DFT & Test

15.6 - 15.7

-

M - Apr 9

Surprise topic

--

W - Apr 11

Review

-

Lab 5 - chip assembly

Th - Apr 12

Exam Preparation Day-No class

F - Apr 13

Exam Preparation Day-No class

Sa - Apr 14

Final exam opens in testing center

--

W - Apr 18

Final exam closes in testing center

--

Library Information

Librarian Information

Name: Peter Zuber

Office: 2321 HBLL

Phone Number: 422-6011

Email: peter_zuber@byu.edu

Reference Desk Information

Name: Science / Maps

Phone Number: 422-2987

Email: science_reference@byu.edu

Hours: M-Th : 8am-9pm; F: 8am-6pm; Sat: 10am-6pm

University Policies

BYU Honor Code

In keeping with the principles of the BYU Honor Code, students are expected to be honest in all of their academic work. Academic honesty means, most fundamentally, that any work you present as your own must in fact be your own work and not that of another. Violations of this principle may result in a failing grade in the course and additional disciplinary action by the university. Students are also expected to adhere to the Dress and Grooming Standards. Adherence demonstrates respect for yourself and others and ensures an effective learning and working environment. It is the university's expectation, and my own expectation in class, that each student will abide by all Honor Code standards. Please call the Honor Code Office at 422-2847 if you have questions about those standards.

Preventing Sexual Discrimination and Harassment

Title IX of the Education Amendments of 1972 prohibits sex discrimination against any participant in an educational program or activity that receives federal funds. The act is intended to eliminate sex discrimination in education. Title IX covers discrimination in programs, admissions, activities, and student-to-student sexual harassment. BYU's policy against sexual harassment extends not only to employees of the university, but to students as well. If you encounter unlawful sexual harassment or gender-based discrimination, please talk to your professor; contact the Equal Employment Office at 422-5895 or 367-5689 (24-hours); or contact the Honor Code Office at 422-2847.

Students with Disabilities

Brigham Young University is committed to providing a working and learning atmosphere that reasonably accommodates qualified persons with disabilities. If you have any disability which may impair your ability to complete this course successfully, please contact the Services for Students with Disabilities Office (422-2767). Reasonable academic accommodations are reviewed for all students who have qualified, documented disabilities. Services are coordinated with the student and instructor by the SSD Office. If you need assistance or if you feel you have been unlawfully discriminated against on the basis of disability, you may seek resolution through established grievance policy and procedures by contacting the Equal Employment Office at 422-5895, D-285 ASB.

Academic Honesty Policy

The first injunction of the BYU Honor Code is the call to be honest. Students come to the university not only to improve their minds, gain knowledge, and develop skills that will assist them in their life's work, but also to build character. President David O. McKay taught that 'character is the highest aim of education' (The Aims of a BYU Education, p. 6). It is the purpose of the BYU Academic Honesty Policy to assist in fulfilling that aim. BYU students should seek to be totally honest in their dealings with others. They should complete their own work and be evaluated based upon that work. They should avoid academic dishonesty and misconduct in all its forms, including but not limited to plagiarism, fabrication or falsification, cheating, and other academic misconduct.

Respectful Environment Policy

"Sadly, from time to time, we do hear reports of those who are at best insensitive and at worst insulting in their comments to and about others... We hear derogatory and sometimes even defamatory comments about those with different political, athletic, or ethnic views or experiences. Such behavior is completely out of place at BYU, and I enlist the aid of all to monitor carefully and, if necessary, correct any such that might occur here, however inadvertent or unintentional."
"I worry particularly about demeaning comments made about the career or major choices of women or men either directly or about members of the BYU community generally. We must remember that personal agency is a fundamental principle and that none of us has the right or option to criticize the lawful choices of another." President Cecil O. Samuelson, Annual University Conference, August 24, 2010

"Occasionally, we ... hear reports that our female faculty feel disrespected, especially by students, for choosing to work at BYU, even though each one has been approved by the BYU Board of Trustees. Brothers and sisters, these things ought not to be. Not here. Not at a university that shares a constitution with the School of the Prophets." Vice President John S. Tanner, Annual University Conference, August 24, 2010